Computer-Aided Digital Design
|Objective of Subject:
||Introduction to hardware description languages and associated methodologies for digital system design and the use of hardware design languages for expressing, simulating, and synthesizing digital designs targeting to ASIC/FPGA.
|Learning Outcome of Subject:
At the completion of the subject, students should be able to:
- Understand the structured design concepts and abstraction levels of IC design.
- Understand the basic concepts of VHDL.
- Understand different VHDL modeling techniques like structural level modeling, RTL modeling , datapath level modeling and algorithmic level modeling.
- Understand different ASIC types and their design processes, standard cell ASIC synthesis, FPGA design paradigm, architecture and synthesis.
- Know how to do top down design with FPGA and write RTL VHDL code for synthesis.
- Know how to do optimization, mapping and delay calculation.
- Ability to acquire and apply fundamental principles of science and engineering(10%)
- Capability to communicate effectively(10%)
- Acquisition of technical competence in specialised areas of engineering discipline(50%)
- Ability to identify, formulate and model problems and find engineering solutions based on a systems approach(15%)
- Understanding of the importance of sustainability and cost-effectiveness in design and development of engineering solutions(5%)
- Ability to work independently as well as with others in a team(10%)
- Lab Experiment - work in group of 2,written and oral assessment at the end of lab(20%)
- Tutorial / Assignment - group assignment,to enhance understanding of basic concepts in lecture(5%)
- Test/Quiz - written exam(15%)
- Final Exam - written exam(60%)
|Teaching and Learning Activities :
||53 hours (lectures,tutorials and laboratory experiments)
||ECP2036: Microprocessor System and Interfacing
- Stefan Sjoholm and Lennart Lind, “VHDL for Designer”, Prentice Hall, 1997
- James A. Armstrong and F. Gail Gray, "VHDL Design", 2nd Edition, Prentice Hall, 2000
- Zainalabedin Navabi, "VHDL: Analysis and Modeling of Digital Systems", 2nd Edition, McGraw Hill, 1998.
- Charles H. Roth, “Digital Systems Design with VHDL”, International Thomson Publishing Asia, 1998.
- Douglas Perry, " VHDL", 3rd Edition, McGraw-Hill, 1998.
- Kevin Skahill, “VHDL for Programmable Logic”, Prentice Hall, 1996.
- Victor P. Nelson, H. Troy Nagle, Bill D. Carrol, J. David Irwin, “Digital Logic Circuit Analysis and Design”, Prentice-Hall, 1995.
Structured Design Concepts
Design constructs, Design Levels, Geometry-based interchange formats, Computer aided electronic system design tools, Schematic circuit capture, Hardware description languages, Design process (simulation, synthesis), Structural design decomposition.
Introduction to VHDL
VHDL language abstractions, Design hierarchies, VHDL component, Lexical description, VHDL source file, Data types, Data objects, Language statements, Concurrent VHDL, Sequential VHDL, Advanced features of VHDL (library, package and subprograms).
VHDL Modeling Techniques
Structural level modeling, Register-Transfer level modeling, Finite State Machine with Datapath level modeling, Algorithmic level modeling.
ASIC and ASIC Design Process
Introduction of ASIC, Types of ASIC, ASIC design process, Standard cell ASIC synthesis, FPGA Design Paradigm, FPGA synthesis, FPGA/CPLD Architectures.
VHDL Design Methodology
Top-down design flow, Verification, simulation alternatives, simulation speed, Formal verification, Recommendations for verification, Writing RTL VHDL code for synthesis, Top-down design with FPGA.
Design for Synthesis
VHDL synthesis, Optimization and mapping, Constraints, Technology library, Delay calculation, Synthesis tool, Synthesis directives.
1. RAM Design
2. ALU modeling of DLX processor in FPGA